A network on a chip (NOC) is a novel integrated circuit architecture that applies a network-based architecture to a single chip to create a unique processing unit. A typical NOC includes a plurality of integrated processor (IP) blocks coupled to one another via the network. NOC processing units typically distribute (i.e., allocate) various parts of a job to different hardware threads of one or more IP blocks to be executed by the one or more IP blocks in the NOC processing unit, where the distribution typically includes transmitting data packets including one or more data words between one or more hardware threads of the NOC. With the number of IP blocks in the standard computer systems expected to rise, efficiently handling workload distribution has become increasingly demanding.
In many conventional NOC architecture systems, data packets are often transmitted over a communication bus/interconnect between IP blocks of the NOC. As the number of IP blocks and hardware threads configured therein continues to rise, the amount of data being communicated over the communication bus of the NOC likewise continues to rise. Improvements in the logic of IP blocks have led to power efficient processing. However, moving data, i.e., communicating data packets has not kept pace with the power reduction improvements in conventional systems. In fact, in many conventional processors, more power is now consumed moving data than performing processing on the data.
A primary source of power consumption in association with data communication results from data signals transitioning between logical “1” and logical “0” values, as the CMOS logic gates typically used in most NOC architecture systems dissipate the most power when switching between logic states. Thus, as the speed of communication bus increases, and the amount of communicated data increases, the overall power consumption of the NOC rises accordingly.
Therefore, a continuing need exists in the art for a manner of increasing the efficiency of on chip communications.